1. Field of the Inventions
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device containing a salicide process.
2. Related Art
A salicide (self-aligned silicide) process is used very often as a way to reduce resistance of a gate, a source and a drain in order to improve characteristics of a transistor. The salicide process means a process including the steps of: forming the gate, the source and the drain of a transistor; forming a metal film on a surface thereof; and providing a silicide layer having low resistance in the regions of the gate, the source and the drain by allowing the metal film to react with a silicon constituting the gate, the source and the drain by means of an annealing process.
Regions formed of a silicon oxide film, such as a LOCOS oxide film and a side wall spacer, hardly react with a metal. Therefore, by selectively removing an unreacted metal film formed on the surface of such regions by means of etching, the silicide layer having low resistance can be selectively formed on the surface of the gate, the source and the drain without conducting a photolithography process or a complex etching process.
FIG. 2(a) to 2(e) show general schematic sectional views illustrating a salicide process in the case of manufacturing a transistor by means of this salicide process. In FIG. 2(a) to 2(e), reference numeral 21 represents a silicon substrate, 22 represents a well formed in the silicon substrate, 23 represents a gate oxide film, 24 represents a LOCOS oxide film, 25 represents a gate made of polysilicon, 26 represents a source, 27 represents a drain, 28 represents a side wall spacer, 29a and 29b each represent a silicide layer formed on a surface of the gate, 30a and 30b each represent a silicide layer formed on the source, 31a and 31b each represent a silicide layer formed on the drain, 32 represents a dielectric film and 33 represents a wiring layer.
Although the following example shows a case in which titanium is used as a metal for forming the silicide layer, cobalt, nickel or the like may also be used as the metal for forming the silicide layer. In such a case, a process for manufacturing the silicide layer is almost the same as in the case of titanium.
First, as shown in FIG. 2(a), a transistor is formed by means of a conventional method. Second, a titanium film 35 is formed by means of a sputtering method, an electron-beam deposition method, a chemical vapor deposition method or the like. Then, an annealing process (first annealing process) is conducted. For this process, a rapid thermal annealing (RTA) method is used in most cases. The annealing process is carried out under an atmosphere of nitrogen gas, so that a titanium nitride layer 34 is formed on a surface of the titanium film 35.
A selective etching process is carried out by using sulfonic acid-hydrogen peroxide or ammonia-hydrogen peroxide to remove the titanium nitride layer 34 and an unreacted titanium remaining on the surface of the side wall spacer or the LOCOS oxide film. In many cases, an annealing process (second annealing process) at high temperature is further conducted. By the first annealing process, a silicide layer of a crystal structure of C49 type having a high resistance is formed. By the second annealing process, the silicide layer of the crystal structure of C49 type is converted into that of a crystal structure of C54 type having a low resistance. The reason why the two annealing processes are carried out before and after the selective etching process is that, if the second annealing process is conducted at a high temperature (usually more than 800.degree. C.) without a selective etching process, surfaces of the side wall spacer and LOCOS oxide film will react violently, making it difficult to remove the unreacted titanium.
As shown in FIG. 2(e), the silicide layer formed on each of the gate, source and drain of an N-type transistor has a thickness smaller than the one formed on each of the gate, source and drain of a P-type transistor.
A sheet resistance of the silicide layer formed by the above process changes depending on the condition in which an impurity is implanted into a region where the salicide is formed. For example, when high-concentration arsenic is used as an N-type impurity, formation of the silicide layer and transformation of the crystal structure of the silicide layer from the one having a high resistance (C49 type) into the one having a low resistance (C54 type) are inhibited. These phenomena occur because arsenic delays the reaction of producing the silicide layer and inhibits the reaction of transformation from the C49 type crystal structure having a high resistance to the C54 type structure having a low resistance. Therefore, according to the conventional process for manufacturing a salicide layer, the sheet resistance of the silicide layer is larger in the N-region wherein arsenic has been implanted than that in the P-region wherein boron (B) or boron difluoride (BF.sub.2) (P-type impurity) has been implanted. These phenomena cause troubles because the effect produced therefrom will be larger according as a size reduction of the device develops. Therefore, there is necessity for solutions to this problem under the design rule of 0.25 .mu.m or less.
In the salicide process, silicon in the gate, source and drain reacts with a metal to form the silicide layer. Therefore, in the case that a junction is shallow because of the size reduction of a transistor, the silicon layers constituting the source and drain between the silicide layer and the substrate or between the silicide layer and the well become thin, so that the salicide layer is not uniform in the N-region and in the P-region. As a result, the junction is partially destroyed and a distance between the silicide layer and the junction becomes short. Accordingly, because of a titanium diffusion, the deterioration of the junction occurs and the amount of leak current increases. Therefore, the formation of a thick silicide layer for reduction of the sheet resistance of the gate, source and drain should be avoided.
For example, in order to decrease the sheet resistance of the region wherein arsenic is implanted, it can be proposed that a titanium film is made thicker to form a thicker silicide layer in the region wherein arsenic is implanted. However, by means of this method, the silicide layer in the region wherein boron is implanted will be thicker than is necessary. Therefore, to avoid the destruction of junction by the silicide layer, it is necessary to make a deep diffusion layer in the region wherein boron is implanted. This increases a short channel effect, so that a performance of the P-type transistor is deteriorated.
Accordingly, there has been a longing for suppressing the increase of the sheet resistance in the region wherein arsenic is implanted without affecting the structure and performance of a P-type transistor. A method involves use of a cobalt silicide layer which is less affected by implantation of arsenic instead of a titanium silicide layer in order to suppress the increase of the sheet resistance. However, the cobalt silicide layer has a disadvantage such that this layer tends to cause a junction leak. In the case of the titanium silicide layer, the sheet resistance of the silicide layer wherein arsenic is implanted can be reduced by a method which involves implantation of silicon ions into the source and drain prior to forming the salicide layer. However, this method leads to increased costs.